Systems and methods are known for testing routing engines which perform message traffic routing in a computer network. Typically, a router packet is generated to target a specific traffic processing operation performed by a hardware, software, or firmware unit under test. An expected output packet is also generated to correspond to the state of the router packet after the specific traffic processing operation has been performed. The expected output packet is then compared to the actual output packet received from the routing engine to determine the success or failure of the test. By generating a series of router packets and corresponding expected output packets, a range of test cases covering the desired traffic processing operations to be tested is produced to fully test the routing engine.
In a routing engine, input packets are received, processed, and then sent on as output packets. Various traffic processing operations may add to, delete from, or otherwise modify the router packet, typically according to a protocol such as the Transmission Control Protocol/Internet Protocol (TCP/IP). In the routing engine, one or more routing chips apply traffic routing instructions to the packet in series according to the traffic processing operations to be performed. Each traffic processing operation includes one or more traffic routing instructions. During a traffic processing operation, many traffic routing instructions may be applied to and may modify the router packet.
When a test case is generated, the expected output packet is generated to correspond to the modifications the router engine will apply to the router packet. The expected output packet reflects the modifications that will be made by the traffic processing operation that the test case is directed to. Each router packet, however, is processed according to a full series of traffic routing instructions occurring as the input packet is processed into an output packet. Therefore, each test case must anticipate not only the modification made by the traffic routing instructions that the test case is directed to, but to all the traffic routing instructions which will modify the packet from the packet through processing as an input packet to the output packet.
Some traffic routing instructions, such as those driven by microcode residing in Application Specific Integrated Circuits (ASICs), result in an unwieldy number of test cases due to the a complex arrangement of control paths exhibited by the traffic routing instructions to be tested. The router packet and the expected output packet must nonetheless be generated to anticipate not only the traffic routing instructions applied by the microcode, but also other traffic routing instructions such as those driven by TCP/IP and other protocols employed by the router engine. The effort required to generate and analyze all the packets of the test cases which result from microcode is substantial. Accordingly, it would be beneficial to provide a system and method to generate router packets directed to test only a set of instructions corresponding to microcode residing in ASICs, without the need to generate router packets and expected output packets which anticipate other traffic routing instructions occurring in the router engine.
A routing chip test case generation system and analyzer operable to generate and analyze test cases for testing microcode allows test cases to be directed to specific microcode operations, such as those executed by an Application Specific Integrated Circuit (ASIC), without burdening the test cases with other operations performed during packet traffic routing in a routing engine. Such ASIC-based test cases are directed to specific microcode operations to be tested by simulating the other non-microcode traffic processing operations performed during packet routing. A router packet is generated to simulate message traffic in a routing engine. The router packet is modified to produce a router test packet that emulates the state of the packet at a point prior to the specific microcode instructions to be tested. A test verification packet is generated to simulate the router test packet after the specific microcode instructions to be tested are applied to the router test packet. The specific microcode instructions are applied to the router test packet to produce a test results packet, and compared to the test verification packet. In this manner, ASICs directed to specific microcode operations can be discretely tested without encompassing or anticipating other traffic routing instructions which typically occur as a packet is processed by the routing engine.
In this manner, the test case generation system generates a router packet directed to testing a specific traffic processing operation in the routing engine. The test case generator determines the processing operations that modify the packet in the routing engine just prior to the execution of the set of test instructions, generates a router test packet indicative of the processing operations prior to the set of test instructions being applied to the router packet, and generates a test verification packet indicative of the set of test instructions being applied to the router test packet.